RISC-V Reddit

Problems adding custom instruction to riscv vector extension in qemu

As stated in the title I want to add a new instruction. It is similar to vfmacc.vv but it is called mfmacc.vv and treats the vectors registers as matrix. I have added the instruction to riscv-opcode and riscv-gnu-toolchain. I wrote a simple program to test if its compiles, it does, with no problem. Then i added the instruction in qemu. Currently it is just vfmacc with another name. When triying to execute it in qemu i come accross the following message: "Illegal instruction (core dumped)". I tried the exact same code with vfmacc and it works.

The changes i conduct in qemu file are:
riscv/insn\_trans/trans\_rvv.c.inc:

GEN_OPFVV_TRANS(mfmacc_vv, opfvv_check)

riscv/helper.h

/*Matrix operation*/
DEF_HELPER_6(mfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)

riscv/insn32.decode

mfmacc_vv 001011 . ..... ..... 001 ..... 1010111 @r_vm

funct6 is 001011 because it does not collide with the rest of vector instructions. And the rest is copied from vfmacc and correspond to the category OPFVV. The following link shows the OPCODE for vector arithmetic instructions and the funct3 for OPFVV.

[https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding](https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding)

riscv/vector\_helper.c

RVVCALL(OPFVV3, mfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
RVVCALL(OPFVV3, mfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
RVVCALL(OPFVV3, mfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
GEN_VEXT_VV_ENV(mfmacc_vv_h, 2)
GEN_VEXT_VV_ENV(mfmacc_vv_w, 4)
GEN_VEXT_VV_ENV(mfmacc_vv_d, 8)

You can check part of the decoded binary:

10248: 0d2672d7 vsetvli t0,a2,e32,m4,ta,ma
1024c: 0207e807 vle32.v v16,(a5)
10250: 02076a07 vle32.v v20,(a4)
10254: 0206ec07 vle32.v v24,(a3)
10258: 2f8a1857 mfmacc.vv v16,v20,v24
1025c: 0207e827 vse32.v v16,(a5)

And the command i use to execute it is:

/usr/local/bin/qemu-riscv64 -cpu rv64,v=true,vlen=128,elen=64,vext_spec=v1.0 simple_matrix

https://redd.it/1kja532
@r_riscv

GitHub

riscv-v-spec/v-spec.adoc at master · riscvarchive/riscv-v-spec

Working draft of the proposed RISC-V V vector extension - riscvarchive/riscv-v-spec

www.tg-me.com/id/RISC V Reddit/com.r_riscv/3291

11 viewsMay 10 at 14:24

Problems adding custom instruction to riscv vector extension in qemu

As stated in the title I want to add a new instruction. It is similar to vfmacc.vv but it is called mfmacc.vv and treats the vectors registers as matrix. I have added the instruction to riscv-opcode and riscv-gnu-toolchain. I wrote a simple program to test if its compiles, it does, with no problem. Then i added the instruction in qemu. Currently it is just vfmacc with another name. When triying to execute it in qemu i come accross the following message: "Illegal instruction (core dumped)". I tried the exact same code with vfmacc and it works.

The changes i conduct in qemu file are:
riscv/insn\_trans/trans\_rvv.c.inc:

GEN_OPFVV_TRANS(mfmacc_vv, opfvv_check)

riscv/helper.h

/*Matrix operation*/
DEF_HELPER_6(mfmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(mfmacc_vv_d, void, ptr, ptr, ptr, ptr, env, i32)

riscv/insn32.decode

mfmacc_vv 001011 . ..... ..... 001 ..... 1010111 @r_vm

funct6 is 001011 because it does not collide with the rest of vector instructions. And the rest is copied from vfmacc and correspond to the category OPFVV. The following link shows the OPCODE for vector arithmetic instructions and the funct3 for OPFVV.

[https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding](https://github.com/riscvarchive/riscv-v-spec/blob/master/v-spec.adoc#sec-arithmetic-encoding)

riscv/vector\_helper.c

RVVCALL(OPFVV3, mfmacc_vv_h, OP_UUU_H, H2, H2, H2, fmacc16)
RVVCALL(OPFVV3, mfmacc_vv_w, OP_UUU_W, H4, H4, H4, fmacc32)
RVVCALL(OPFVV3, mfmacc_vv_d, OP_UUU_D, H8, H8, H8, fmacc64)
GEN_VEXT_VV_ENV(mfmacc_vv_h, 2)
GEN_VEXT_VV_ENV(mfmacc_vv_w, 4)
GEN_VEXT_VV_ENV(mfmacc_vv_d, 8)

You can check part of the decoded binary:

10248: 0d2672d7 vsetvli t0,a2,e32,m4,ta,ma
1024c: 0207e807 vle32.v v16,(a5)
10250: 02076a07 vle32.v v20,(a4)
10254: 0206ec07 vle32.v v24,(a3)
10258: 2f8a1857 mfmacc.vv v16,v20,v24
1025c: 0207e827 vse32.v v16,(a5)

And the command i use to execute it is:

/usr/local/bin/qemu-riscv64 -cpu rv64,v=true,vlen=128,elen=64,vext_spec=v1.0 simple_matrix

https://redd.it/1kja532
@r_riscv

BY RISC-V Reddit